Updated on 2026/03/07

写真a

 
YAMAZAKI KOJI
 
Organization
Undergraduate School School of Information and Communication Associate Professor
Title
Associate Professor
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Degree

  • 工学博士 ( 1994.3   明治大学 )

Research Areas

  • Other / Other  / VLSI CAD

Education

  • Meiji University   Graduate School, Division of Engineering   Electrical Engineering

    - 1994.3

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    Country/Region: Japan

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  • Meiji University   Graduate School, Division of Engineering   Electrical Engineering

    - 1991.3

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    Country/Region: Japan

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Research History

  • Meiji University   School of Information and Communication   Associate Professor

    2005.4

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  • Meiji University   School of Information and Communication   Lecturer

    2004.4 - 2005.3

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  • Meiji University   School of Science and Technology   Lecturer

    1994.4 - 2004.3

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Professional Memberships

Papers

  • Fault Diagnosis for Logic Circuits - Development of Methods for Identifying Fault Locations based on Output Responses -

    Yuzo Takamatsu, Yasuo Sato, Hiroshi Takahashi, Yoshinobu Higami

    J94-D ( 1 )   266-279   2011.1

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  • A Method for Locating Open Faults by Using a Fault Excitation Function

    Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Takashi Aikyo, Hiroyuki Yotsuyanagi, Masaki Hashizume, Yuzo Takamatsu

    J93-D ( 11 )   2416-2425   2010.11

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  • A Novel Approach for Improving the Quality of Open Fault Diagnosis

    VLSI Design   85-90   2009.1

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  • オープン故障診断の性能向上について

    電子情報通信学会技術研究報告   108 ( 99 )   20-34   2008.6

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  • A Method of Locating Open Faults on Incompletely Identified Pass/Fail Information

    IEICE,Trans.Information and Systems   E91-D ( 3 )   661-666   2008.3

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  • Fanout-Based Fault Diagnosis for Open Faults On Pass/Fail Information

    Yuzo Takamatsu

    IEEE computer society Proc.of 15th ATS   349-353   2006.11

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  • Post-BIST Fault Diangosis for Multiple Stuck-at Faults

    Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato

    Proc. IEEE International Silicon Debug and Diaganosis   1-6   2005.11

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  • On the fault diagnosis in the presence of unknown fault models usign pass/fail infomation

    Takamatsu, Y., Seiyama, T., Takahashi, H., Higami, Y., Yamazaki, K.

    IEEE International Symposium on Circuits and System ISCAS2005   2987-2990   2005.5

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  • Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset

    T.Yamada, T.Kotake, H.Takahashi and K.Yamazaki

    IEEE Computer Society, Proc. of 8th ATS   269-274   1999.11

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  • CMOS回路における短絡故障の一モデルとそのテスト生成法

    高松雄三 塩坂知子 山田輝彦 山崎浩二

    電子通信情報学会論文誌D-1   J81 ( 6 )   872-879   1998.6

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  • An Approach to Diagnose Logical Faults in Partially Observable Sequential Circuits

    K.Yamazaki, T.Yamada

    IEEE Computer Society, Proc. of 6th ATS   168-173   1997.11

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  • 組合せ回路における論理故障のシミュレーションに基づく一診断法

    山崎浩二 山田輝彦

    電子通信情報学会論文誌D-1   J79 ( 12 )   1123-1130   1996.12

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  • An approach of diagnosing single bridging faults in CMOS combinational circuits

    K.Yamazaki, T.Yamada

    IEEE computer societyProc.of 3rd ATS   88-93   1994.11

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  • 組合せ回路におけるn線間の短絡故障の診断法

    山崎浩二,山田輝彦

    電子情報通信学会電子情報通信学会論文誌D-1   J77-D-1   77-85   1994.1

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  • SIFLAP-G:A method of diagnosing gate-level faults in combinational circuits

    K.Yamazaki, T.Yamada

    IEICE Trans. Inf. & syst.   E76-D   826-831   1993.7

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  • A method of diagnosing logical faults in commbinational circuits

    K.Yamazaki, T.Yamada

    IEEE computer societyProc.of 1st ATS   170-175   1992.11

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  • 組み合わせ回路における単一短絡故障の診断法

    山田輝彦 山崎浩二

    電子情報通信学会電子情報通信学会論文誌D-1   J74-d-1   58-64   1991.1

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MISC

  • 故障シミュレータとテスト生成手法を併用したオープン故障の診断法

    山崎浩二

    明治大学 情報コミュニケーション学部紀要   ( 1 )   207-216   2005.3

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  • 組合せ回路の単一短絡故障に対する検出率の一評価法

    山崎浩二 山田輝彦

    明治大学 理工学部研究報告   62 ( 6 )   43-48   1992.3

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Presentations

  • 「しきい値関数を利用したファンナウト中のオープン故障の診断法」

    FTC研究会  2010.7 

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  • 「テストパターンの診断分解能に及ぼす影響」

    "◎村田裕*, 菱田和宏*, 山崎浩二(専任講師), 山田輝彦(教授)"

    1998.3 

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  • 「2重故障シミュレータを用いた組合せ回路における多重論理故障の診断法」

    "◎佐々木智則*, 山崎浩二(専任講師), 山田輝彦(教授)"

    1998.3 

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  • 「誤り経路追跡と故障シミュレーションを用いた順序回路における単一故障の一診断法」

    "◎山崎浩二(専任講師), 山田輝彦(教授)"

    1997.12 

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  • 「部分可観測な組合せ論理回路における論理故障の診断法」

    FTC 研究会  1996.7 

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  • 「順序回路におけるプローブを用いた論理故障の一診断法」

    LSI テスティングシンポジウム  1995.12 

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  • A simple technique for locating gate-level faults in combinational circuits

    "T.Yamada, K.Yamazaki and E.J.McCluskey"

    IEEE computer societyProc.of 4th ATS  1995.11  IEEE computer societyProc.of 4th ATS

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  • A simple technique for locating gate-level faults in CMOS combinational circuits

    4th Asian Test Symposium  1995.11 

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Research Projects

  • Fault location for partially open faults

    2009 - 2011

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  • Fault location for open faults

    2006 - 2008

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  • Fault location under BIST environment

    2003 - 2005

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  • Fault locaiont for delay faults on VLSI

    1999

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  • Fault location for logical faults on VLSI

    1994

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