Updated on 2026/07/16

写真a

 
MIYAJIMA TAKAAKI
 
Organization
Undergraduate School School of Science and Technology Senior Assistant Professor
Title
Senior Assistant Professor
Homepage
https://sites.google.com/view/hppcs-lab
External link

Degree

  • Ph.D ( 2015.3   Keio University )

  • MS.c ( 2011.3   Keio University )

Research Interests

  • ウェハスケールコンピューティング

  • 計算機システム

  • リコンフィギャラブルコンピューティング

  • 高性能計算

Research Areas

  • Informatics / High-performance computing

  • Informatics / Computer systems

Education

  • Keio University   Graduate School of Science and Technology

    2011.4 - 2014.9

    　 More details

    Country/Region： Japan

    researchmap

  • Keio University   Graduate School of Science and Technology

    2009.4 - 2011.3

    　 More details

    Country/Region： Japan

    researchmap

  • Meiji University   School of Science and Technology

    2004.4 - 2009.3

    　 More details

    Country/Region： Japan

    researchmap

Research History

  • Meiji University   School of Science and Technology Department of Computer Science   Senior Assistant Professor

    2021.4

    　 More details

    Country/Region：Japan

    researchmap

  • RIKEN   RIKEN Center for Computational Science

    2018.4 - 2021.3

    　 More details

    Country/Region：Japan

    researchmap

  • Japan Aerospace Exploration Agency

    2014.10 - 2018.3

    　 More details

    Country/Region：Japan

    researchmap

Professional Memberships

Papers

▼display all

MISC

  • csDF:Cerebras CS-2向け疑似倍精度浮動小数点演算ライブラリの実装

    村上魁, 長島令旺, 中村暁, 松崎竜之介, 吉井一友, 椋木大地, 宮島敬明

    情報処理学会研究報告(Web)   2025 ( ARC-263 )   2025

    　More details

Presentations

  • Wafer-Scale Computing for HPC: Current State, Opportunities, and Community Building

    Takaaki Miyajima, Kazutomo Yoshii, Robert Underwood, Michael James

    Wafer-Scale Computing for HPC: Current State, Opportunities, and Community Building 

    　More details

    Event date： 2026.1

    Language：English   Presentation type：Symposium, workshop panel (public)  

    File： 00 BoF welcome.pdf

    researchmap

  • Cerebras アーキテクチャ Deep Dive Invited

    宮島敬明

    Cerebras アーキテクチャ Deep Dive 主催 : 東京エレクトロン デバイス株式会社  2024.7 

    　More details

    Language：Japanese   Presentation type：Public lecture, seminar, tutorial, course, or other speech  

    File： Cerebras アーキテクチャ Deep Dive 公開版.pdf

    researchmap

Awards

  • Outstanding Student Poster Award

    2026.1   SCA/HPCAsia2026   Towards Acceleration of Sparse Matrix-Vector Multiplication on the Cerebras CS-2

    Saho Orihara, Kouki Sakai, Takaaki Miyajima

    　More details

  • 学生優秀発表賞

    2022   IPSJ ハイパフォーマンスコンピューティング研究発表会   Cerebras CS-2を用いたリダクション処理の実装と性能評価

    福岡 伶音, 宮島 敬明

    　More details

Research Projects

  • グラフ構造データ処理を加速するウェハースケール・コンピューティング

    Grant number：26K02920  2026.4 - 2030.3

    日本学術振興会  科学研究費助成事業  基盤研究(B)

    小林 諒平, 宮島 敬明

    　 More details

    Grant amount：\24700000 （ Direct Cost: \19000000 、 Indirect Cost：\5700000 ）

    researchmap

  • Performance estimation of scientific computing of an extremely large AI accelerator with 850,000 PEs.

    Grant number：24K14972  2024.4 - 2027.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (C)

    　 More details

    Grant amount：\4550000 （ Direct Cost: \3500000 、 Indirect Cost：\1050000 ）

    researchmap

  • Creation of Scalable Computers and their System Software for Post-Moore Era

    Grant number：20H00593  2020.4 - 2024.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (A)

    Sano Kentaro

    　 More details

    Grant amount：\44720000 （ Direct Cost: \34400000 、 Indirect Cost：\10320000 ）

    As a computation mechanism and model, we developed an FPGA cluster as a dataflow architecture (DFA) prototype system, researched coarse-grained reconfigurable arrays (CGRA) as DFA, and researched dataflow computation with FPGAs. As programming models and system software, we researched a programming scheme for asynchronous operation of dataflow tasks between a host CPU and FPGAs, and their task scheduler. We also researched OpenACC/OpenMP compilers for dataflow computation on FPGAs.
    As an application, we researched DFA for graph processing, convex hull computing, stencil computation, and so on.

    researchmap

  • A research and development of an advanced CFD algorithm for next generation multi FPGA system.

    Grant number：19K20282  2019.4 - 2022.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Early-Career Scientists

    Miyajima Takaaki

    　 More details

    Grant amount：\4290000 （ Direct Cost: \3300000 、 Indirect Cost：\990000 ）

    A proposal to make a search for neighbour particles in MPS method into a form of data flow was published at an international conference. The proposal was also implemented on FPGA and evaluated. It is shown that the processing time on Arria10 FPGA slightly out-perform it on multi-core CPU. We found that there is room for improvement in a proposed model to estimate circuit area. Regarding multiple FPGA, a bridged data transfer with CPU was proposed and evaluated. An evaluation shows that although the bridged data transfer is more flexible than FPGA dedicated data transfer, bandwidth is lower than FPGA-dedicated one. We are now considering using the latter one to achieve higher performance.

    researchmap

  • Creation of non-Neumann FPGA Overlay Architecture for Innovating HPC

    Grant number：17H01706  2017.4 - 2020.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Scientific Research (B)

    Sano Kentaro

    　 More details

    Grant amount：\18720000 （ Direct Cost: \14400000 、 Indirect Cost：\4320000 ）

    We have developed fundamental technologies of non-Neumann overlay architecture to exploit FPGAs, which are circuit reconfigurable semiconductor devices, in order to achieve next-generation HPC systems instead of Neumann architectures which are slowing down in performance improvement. With a prototype of FPGA cluster, we have constructed its hardware and software framework, and developed a high-level synthesis compiler for computing problems to be implemented as data-flow circuits on FPGAs. We showed that a pipelining method can increase performance of several computing problems according to the number of FPGAs. This demonstrates that relatively low-power FPGAs can achieve high-performance and scalable computing.

    researchmap

  • An acceleration of hall thruster simulation

    Grant number：16K16064  2016.4 - 2019.3

    Japan Society for the Promotion of Science  Grants-in-Aid for Scientific Research  Grant-in-Aid for Young Scientists (B)

    Miyajima Takaaki

    　 More details

    Grant amount：\2210000 （ Direct Cost: \1700000 、 Indirect Cost：\510000 ）

    Contribution of this research is present a technique that shortens the processing time of the MPS method. MPS method can simulate raindrops or flowing water which were difficult in the past. It is known that the kernel of the MPS method is time-consuming. We proposed an optimization technique which takes physics of MPS method into consideration to reduce the processing time. On top of that, we implemented and evaluate a proposed technique on multiple parallel processing machines. Processing time on CPU(Xeon Gold 6150x2) is 35.1[ms], GPU(P100NVL) is 6.8[ms], and KNL-7210 is 104.1[ms], respectively. We also conducted a preliminary evaluation on the GPU cluster and found that additional optimizations are required to achieve better scalability.

    researchmap

▼display all